`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:30:08 10/21/2010 
// Design Name: 
// Module Name:    counter_ROM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module counter_ROM(
		input enable,
		input clk,
		input [9:0] addr,
		output [15:0] data
		
    );
	
		RAMB16_S18 # (
		.INIT( {2'h0 , 16'h0000} ), 						// Value of output RAM registers on Port A at startup
		.SRVAL( 18'h04000 ), 								// Port A output value upon SSR assertion
		.WRITE_MODE( "NO_CHANGE" ),							// "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"

         // The following INIT_xx declarations specify the initial contents of the RAM
         //Address 0 to 255
        .INIT_00(256'h000E_000D_000C_000B_000A_0009_0008_0007_0006_0005_0004_0003_0002_0001_1C00_0C00),
        .INIT_01(256'h001E_001D_001C_001B_001A_0019_0018_8017_0016_0015_0014_0013_0012_0011_0010_000F),
        .INIT_02(256'h002E_002D_002C_002B_002A_0029_0028_8027_0026_0025_0024_0023_0022_0021_0020_001F),
        .INIT_03(256'h003E_003D_003C_003B_003A_0039_0038_8037_0036_0035_0034_0033_0032_0031_0030_002F),
        .INIT_04(256'h004E_004D_004C_004B_004A_0049_0048_0047_0046_0045_0044_0043_0042_0041_0040_003F),
        .INIT_05(256'h005E_005D_005C_005B_005A_0059_0058_0057_0056_0055_0054_0053_0052_0051_0050_004F),
        .INIT_06(256'h006E_006D_006C_006B_006A_0069_0068_0067_0066_0065_0064_0063_0062_0061_0060_005F),
        .INIT_07(256'h007E_007D_007C_007B_007A_0079_0078_0077_0076_0075_0074_0073_0072_0071_0070_006F),
        .INIT_08(256'h008E_008D_008C_008B_008A_0089_0088_0087_0086_0085_0084_0083_0082_0081_0080_007F),
        .INIT_09(256'h009E_009D_009C_009B_009A_0099_0098_0097_0096_0095_0094_0093_0092_0091_0090_008F),
        .INIT_0A(256'h00AE_00AD_00AC_00AB_00AA_00A9_00A8_00A7_00A6_00A5_00A4_00A3_00A2_00A1_00A0_009F),
        .INIT_0B(256'h00BE_00BD_00BC_00BB_00BA_00B9_00B8_00B7_00B6_00B5_00B4_00B3_00B2_00B1_00B0_00AF),
        .INIT_0C(256'h00CE_00CD_00CC_00CB_00CA_00C9_00C8_00C7_00C6_00C5_00C4_00C3_00C2_00C1_00C0_00BF),
        .INIT_0D(256'h00DE_00DD_00DC_00DB_00DA_00D9_00D8_00D7_00D6_00D5_00D4_00D3_00D2_00D1_00D0_00CF),
        .INIT_0E(256'h00EE_00ED_00EC_00EB_00EA_00E9_00E8_00E7_00E6_00E5_00E4_00E3_00E2_00E1_00E0_00DF),
        .INIT_0F(256'h00FE_00FD_00FC_00FB_00FA_80F9_00F8_00F7_00F6_00F5_00F4_00F3_00F2_00F1_00F0_00EF),
        //Address 256 to 511
        .INIT_10(256'h010E_010D_010C_010B_010A_0109_0108_0107_0106_0105_0104_0103_0102_0101_0100_00FF),
        .INIT_11(256'h011E_011D_011C_011B_011A_0119_0118_0117_0116_0115_0114_0113_0112_0111_0110_010F),
        .INIT_12(256'h012E_012D_012C_012B_012A_0129_0128_0127_0126_0125_0124_0123_0122_0121_0120_011F),
        .INIT_13(256'h013E_013D_013C_013B_013A_0139_0138_0137_0136_0135_0134_0133_0132_0131_0130_012F),
        .INIT_14(256'h014E_014D_014C_014B_014A_0149_0148_0147_0146_0145_0144_0143_0142_0141_0140_013F),
        .INIT_15(256'h015E_015D_015C_015B_015A_0159_0158_0157_0156_0155_0154_0153_0152_0151_0150_014F),
        .INIT_16(256'h016E_016D_016C_016B_016A_0169_0168_0167_0166_0165_0164_0163_0162_0161_0160_015F),
        .INIT_17(256'h017E_017D_017C_017B_017A_0179_0178_0177_0176_0175_0174_0173_0172_0171_0170_016F),
        .INIT_18(256'h018E_018D_018C_018B_018A_0189_0188_0187_0186_0185_0184_0183_0182_0181_0180_017F),
        .INIT_19(256'h019E_019D_019C_019B_019A_0199_0198_0197_0196_0195_0194_0193_0192_0191_0190_018F),
        .INIT_1A(256'h01AE_01AD_01AC_01AB_01AA_01A9_01A8_01A7_01A6_01A5_01A4_01A3_01A2_01A1_01A0_019F),
        .INIT_1B(256'h01BE_01BD_01BC_01BB_01BA_01B9_01B8_01B7_01B6_01B5_01B4_01B3_01B2_01B1_01B0_01AF),
        .INIT_1C(256'h01CE_01CD_01CC_01CB_01CA_01C9_01C8_01C7_01C6_01C5_01C4_01C3_01C2_01C1_01C0_01BF),
        .INIT_1D(256'h01DE_01DD_01DC_01DB_01DA_01D9_01D8_01D7_01D6_01D5_01D4_01D3_01D2_01D1_01D0_01CF),
        .INIT_1E(256'h01EE_01ED_01EC_01EB_01EA_01E9_01E8_01E7_01E6_01E5_01E4_01E3_01E2_01E1_01E0_01DF),
        .INIT_1F(256'h01FE_01FD_01FC_01FB_01FA_01F9_01F8_01F7_01F6_01F5_01F4_01F3_01F2_01F1_01F0_01EF),
        //Address 512 to 767
        .INIT_20(256'h020E_020D_020C_020B_020A_0209_0208_0207_0206_0205_0204_0203_0202_0201_0200_01FF),
        .INIT_21(256'h021E_021D_021C_021B_021A_0219_0218_0217_0216_0215_0214_0213_0212_0211_0210_020F),
        .INIT_22(256'h022E_022D_022C_022B_022A_0229_0228_0227_0226_0225_0224_0223_0222_0221_0220_021F),
        .INIT_23(256'h023E_023D_023C_023B_023A_0239_0238_0237_0236_0235_0234_0233_0232_0231_0230_022F),
        .INIT_24(256'h024E_024D_024C_024B_024A_0249_0248_0247_0246_0245_0244_0243_0242_0241_0240_023F),
        .INIT_25(256'h025E_025D_025C_025B_025A_0259_0258_0257_0256_0255_0254_0253_0252_0251_0250_024F),
        .INIT_26(256'h026E_026D_026C_026B_026A_0269_0268_0267_0266_0265_0264_0263_0262_0261_0260_025F),
        .INIT_27(256'h027E_027D_027C_027B_027A_0279_0278_0277_0276_0275_0274_0273_0272_0271_0270_026F),
        .INIT_28(256'h028E_028D_028C_028B_028A_0289_0288_0287_0286_0285_0284_0283_0282_0281_0280_027F),
        .INIT_29(256'h029E_029D_029C_029B_029A_0299_0298_0297_0296_0295_0294_0293_0292_0291_0290_028F),
        .INIT_2A(256'h02AE_02AD_02AC_02AB_02AA_02A9_02A8_02A7_02A6_02A5_02A4_02A3_02A2_02A1_02A0_029F),
        .INIT_2B(256'h02BE_02BD_02BC_02BB_02BA_02B9_02B8_02B7_02B6_02B5_02B4_02B3_02B2_02B1_02B0_02AF),
        .INIT_2C(256'h02CE_02CD_02CC_02CB_02CA_02C9_02C8_02C7_02C6_02C5_02C4_02C3_02C2_02C1_02C0_02BF),
        .INIT_2D(256'h02DE_02DD_02DC_02DB_02DA_02D9_02D8_02D7_02D6_02D5_02D4_02D3_02D2_02D1_02D0_02CF),
        .INIT_2E(256'h02EE_02ED_02EC_02EB_02EA_02E9_02E8_02E7_02E6_02E5_02E4_02E3_02E2_02E1_02E0_02DF),
        .INIT_2F(256'h02FE_02FD_02FC_02FB_02FA_02F9_02F8_02F7_02F6_02F5_02F4_02F3_02F2_02F1_02F0_02EF),
        //Address 768 to 1023
        .INIT_30(256'h030E_030D_030C_030B_030A_0309_0308_0307_0306_0305_0304_0303_0302_0301_0300_02FF),
        .INIT_31(256'h031E_031D_031C_031B_031A_0319_0318_0317_0316_0315_0314_0313_0312_0311_0310_030F),
        .INIT_32(256'h032E_032D_032C_032B_032A_0329_0328_0327_0326_0325_0324_0323_0322_0321_0320_031F),
        .INIT_33(256'h033E_033D_033C_033B_033A_0339_0338_0337_0336_0335_0334_0333_0332_0331_0330_032F),
        .INIT_34(256'h034E_034D_034C_034B_034A_0349_0348_0347_0346_0345_0344_0343_0342_0341_0340_033F),
        .INIT_35(256'h035E_035D_035C_035B_035A_0359_0358_0357_0356_0355_0354_0353_0352_0351_0350_034F),
        .INIT_36(256'h036E_036D_036C_036B_036A_0369_0368_0367_0366_0365_0364_0363_0362_0361_0360_035F),
        .INIT_37(256'h037E_037D_037C_037B_037A_0379_0378_0377_0376_0375_0374_0373_0372_0371_0370_036F),
        .INIT_38(256'h038E_038D_038C_038B_038A_0389_0388_0387_0386_0385_0384_0383_0382_0381_0380_037F),
        .INIT_39(256'h039E_039D_039C_039B_039A_0399_0398_0397_0396_0395_0394_0393_0392_0391_0390_038F),
        .INIT_3A(256'h03AE_03AD_03AC_03AB_03AA_03A9_03A8_03A7_03A6_03A5_03A4_03A3_03A2_03A1_03A0_039F),
        .INIT_3B(256'h03BE_03BD_03BC_03BB_03BA_03B9_03B8_03B7_03B6_03B5_03B4_03B3_03B2_03B1_03B0_03AF),
        .INIT_3C(256'h03CE_03CD_03CC_03CB_03CA_03C9_03C8_03C7_03C6_03C5_03C4_03C3_03C2_03C1_03C0_03BF),
        .INIT_3D(256'h03DE_03DD_03DC_03DB_03DA_03D9_03D8_03D7_03D6_03D5_03D4_03D3_03D2_03D1_03D0_03CF),
        .INIT_3E(256'h03EE_03ED_03EC_03EB_03EA_03E9_03E8_03E7_03E6_03E5_03E4_03E3_03E2_03E1_03E0_03DF),
        .INIT_3F(256'h03FE_03FD_03FC_03FB_03FA_03F9_03F8_03F7_03F6_03F5_03F4_03F3_03F2_03F1_03F0_03EF),

      // The next set of INITP_xx are for the parity bits
      // Address 0 to 255
		.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
		.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
      // Address 256 to 511
		.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
		.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
      // Address 512 to 767
		.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
		.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
      // Address 768 to 1023
		.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
		.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
	
	) t_cnt_ROM0 (
		.DI( 16'b0 ),										//data in [15:0]			
		.DIP( 2'b0 ),										//data in [17:16] parity
		.ADDR( addr[9:0] ),						//address bus [9:0]		
		.EN( enable ),										//enable signal			
		.WE( 1'b0 ),										//write enable signal	
		.SSR( 1'b0 ),										//set/reset signal			
		.CLK( clk ),									//clock signal			
		.DO( data[15:0] ),	//data out [15:0]			
		.DOP( )											//data out [17:16] parity				
	);



endmodule
